EP1SGX10DF672C6 Datasheet, PDF (39/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Figure 2–24. BIST PRBS Data Path
Deserializer
Word
Aligner
BIST PRBS
Verifier
Channel
Aligner
Clock
Recovery
Unit
Rate
Matcher
8B/10B
Decoder
Stratix GX Transceivers
Byte
Deserializer
BIST
Incremental
Verifier
Phase
Compensation
FIFO
Serializer
Active Path
Non-active Path
8B/10B
Encoder
BIST PRBS
Generator
Byte
Serializer
Phase
Compensation
FIFO
BIST
Generator
Figure 2–25. BIST Incremental Data Path
Deserializer
Word
Aligner
BIST PRBS
Verifier
Channel
Aligner
Clock
Recovery
Unit
Rate
Matcher
8B/10B
Decoder
Byte
Deserializer
BIST
Incremental
Verifier
Phase
Compensation
FIFO
Serializer
Active Path
Non-active Path
8B/10B
Encoder
BIST PRBS
Generator
Byte
Serializer
Phase
Compensation
FIFO
BIST
Generator
Table 2–9 shows the BIST data output and verifier alignment pattern.
Table 2–9. BIST Data Output & Verifier Alignment Pattern (Part 1 of 2)
BIST Mode
PRBS 8-bit
PRBS 10-bit
2⁸ – 1
2¹⁰ – 1
Output
Polynomials
x⁸ + x⁷ + x⁵ + x³ + 1
x¹⁰ + x⁷ + 1
Verifier Word Alignment Pattern
1000000011111111
1111111111
Altera Corporation
June 2006
2–29
Stratix GX Device Handbook, Volume 1