EP1SGX10DF672C6 Datasheet, PDF (264/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

High-Speed I/O Specification
Table 6–87. High-Speed I/O Specifications (Part 4 of 4) Notes (1), (2)
Symbol
Conditions
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
Output t_FALL
t_DUTY
t_LOCK
LVDS
HyperTransport
technology
LVPECL
PCML
LVDS (J = 2 through
10)
LVDS (J =1) and
LVPECL, PCML,
HyperTransport
technology
All
80 110 120 80 110 120 80 110 120 ps
110 170 200 110 170 200 110 170 200 ps
90 130 160 90 130 160 100 135 160 ps
105 140 175 105 140 175 110 145 175 ps
47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 %
45 50 55 45 50 55 45 50 55 %
100
100
100 μs
Notes to Table 6–87:
(1) When J = 4, 7, 8, and 10, the SERDES block is used.
(2) When J = 2 or J = 1, the SERDES is bypassed.
(3) Number of parallel CLK cycles.
(4) Number of repetitions.
PLL Timing
Tables 6–88 through 6–90 describe the Stratix GX device enhanced PLL
specifications.
Table 6–88. Enhanced PLL Specifications for -5 Speed Grades (Part 1 of 2)
Symbol
f_IN
f_INDUTY
f_EINDUTY
t_INJITTER
t_EINJITTER
t_FCOMP
f_OUT
f_{OUT_EXT}
Parameter
Min Typ
Input clock frequency
3 (1)
Input clock duty cycle
40
External feedback clock input duty
40
cycle
Input clock period jitter
External feedback clock period jitter
External feedback clock compensation
time (3)
Output frequency for internal global or 0.3
regional clock
Output frequency for external clock (2) 0.3
Max
684
60
60
±200 (2)
±200 (2)
6
500
526
Unit
MHz
%
%
ps
ps
ns
MHz
MHz
6–62
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006