EP1SGX10DF672C6 Datasheet, PDF (67/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

4. Stratix GX Architecture
SGX51004-1.0
Logic Array
Blocks
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, local
interconnect, LUT chain, and register chain connection lines. The local
interconnect transfers signals between LEs in the same LAB. LUT chain
connections transfer the output of one LE’s LUT to the adjacent LE for fast
sequential LUT connections within the same LAB. Register chain
connections transfer the output of one LE’s register to the adjacent LE’s
register within an LAB. The Quartus^® II Compiler places associated logic
within an LAB or adjacent LABs, allowing the use of local, LUT chain,
and register chain connections for performance and area efficiency.
Figure 4–1 shows the Stratix^® GX LAB.
Figure 4–1. Stratix GX LAB Structure
Row Interconnects of
Variable Speed & Length
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Altera Corporation
February 2005
Direct link
interconnect from
adjacent block
Local Interconnect LAB
Direct link
interconnect to
adjacent block
Three-Sided Architecture—Local
Interconnect is Driven from Either Side by
Columns & LABs, & from Above by Rows
Column Interconnects of
Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, M512 RAM blocks,
4–1