|
EP1SGX10DF672C6 Datasheet, PDF (255/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet | |||
|
◁ |
DC & Switching Characteristics
The scaling factors for output pin timing in Table 6â80 are shown in units
of time per pF unit of capacitance (ps/pF). Add this delay to the
combinational timing path for output or bidirectional pins in addition to
the âI/O Adderâ delays shown in Tables 6â72 through 6â77 and the âIOE
Programmable Delaysâ in Tables 6â78 and 6â79.
Table 6â80. Output Delay Adder for Loading on LVTTL/LVCMOS Output Buffers
LVTTL/LVCMOS Standards
Conditions
Parameter
Value
Drive Strength
24 mA
16 mA
12 mA
8 mA
4 mA
2 mA
Output Pin Adder Delay (ps/pF)
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL
15
â
â
-
25
18
â
â
30
25
25
â
50
35
40
35
60
â
â
80
â
75
120
160
SSTL/HSTL Standards
LVCMOS
8
â
15
20
30
60
Conditions
Class I
Class II
Output Pin Adder Delay (ps/pF)
SSTL-3
SSTL-2
SSTL-1.8 1.5-V HSTL
25
25
25
25
25
20
25
20
GTL+/GTL/CTT/PCI Standards
1.8-V HSTL
25
20
Conditions
Output Pin Adder Delay (ps/pF)
Parameter
Value
GTL+
GTL
CTT
PCI
AGP
VC C I O voltage
3.3 V
18
18
25
20
20
level
2.5 V
15
18
-
-
-
Altera Corporation
June 2006
6â53
Stratix GX Device Handbook, Volume 1
|
▷ |