EP1SGX10DF672C6 Datasheet, PDF (65/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Source-Synchronous Signaling With DPA
To manage the alignment procedure, a state machine should be built in
the FPGA logic array to generate the realignment signal. The following
guidelines outline the requirements for this state machine.
■ The design must include an input synchronizing register to ensure
that data is synchronized to the ×W/J clock.
■ After the state machine, use another synchronizing register to
capture the generated rx_channel_data_align signal and
synchronize it to the ×W/J clock.
■ Because the skew in the path from the output of this synchronizing
register to the PLL is undefined, the state machine must generate a
pulse that is high for two W/J clock periods.
■ To guarantee the state machine does not incorrectly generate
multiple rx_channel_data_align pulses to shift a single bit, the
state machine must hold the rx_channel_data_align signal low
for at least three ×1 clock periods between pulses.
Altera Corporation
August 2005
3–15
Stratix GX Device Handbook, Volume 1