EP1SGX10DF672C6 Datasheet, PDF (176/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

I/O Structure
Figure 4–68. Simplified Diagram of the DQS Phase-Shift Circuitry
Input
Reference
Clock
Phase
Comparator
Up/Down
Counter
Delay Chains
6
Control Signals
to DQS Pins
See the External Memory Interfaces chapter of the Stratix GX Device
Handbook, Volume 2 for more information on external memory interfaces.
Programmable Drive Strength
The output buffer for each Stratix GX device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL and
LVCMOS standard has several levels of drive strength that the user can
control. SSTL-3 class I and II, SSTL-2 class I and II, HSTL class I and II, and
3.3-V GTL+ support a minimum setting, the lowest drive strength that
guarantees the I_OH/I_OL of the standard. Using minimum settings
provides signal slew rate control to reduce system noise and signal
overshoot.
4–110
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005