EP1SGX10DF672C6 Datasheet, PDF (91/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
Figure 4–14. M512 RAM Block Control Signals
Dedicated
8
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
inclocken
outclocken
wren
outclr
inclock
outclock
rden
inclr
Altera Corporation
February 2005
4–25
Stratix GX Device Handbook, Volume 1