EP1SGX10DF672C6 Datasheet, PDF (28/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Deserializer (Serial-to-Parallel Converter)
The deserializer converts the serial stream into a parallel 8- or 10-bit data
bus. The deserializer receives the least significant bit first. Figure 2–14 is
a diagram of the deserializer.
Figure 2–14. Deserializer
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
10
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
High-speed
serial clock
Low-speed
parallel clock
Word Aligner
The word aligner aligns the incoming data based on the specific byte
boundaries. The word aligner has three customizable modes of operation:
bit-slip mode, 16-bit mode, and 10-bit mode, the last of which is available
for the basic and SONET modes. The word aligner also has two
non-customizable modes of operation, which are the XAUI and GIGE
modes.
Figure 2–15 shows the word aligner in bit-slip mode.
2–18
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006