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EP1SGX10DF672C6 Datasheet, PDF (256/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet | |||
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Timing Model
Maximum Input & Output Clock Rates
Tables 6â81 through 6â83 show the maximum input clock rate for column
and row pins in Stratix GX devices.
Table 6â81. Stratix GX Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins
I/O Standard
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1Ã
AGP 2Ã
CTT
Differential HSTL
LVDS
LVPECL
PCML
HyperTransport technology
-5 Speed Grade -6 Speed Grade -7 Speed Grade
422
422
390
422
422
390
422
422
390
422
422
390
422
422
390
300
250
200
300
250
200
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
400
350
300
422
422
390
422
422
390
422
422
390
422
422
390
422
422
390
300
250
200
400
350
300
645
645
622
645
645
622
300
275
275
500
500
450
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
6â54
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006
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