EP1SGX10DF672C6 Datasheet, PDF (92/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

TriMatrix Memory
Figure 4–15. M512 RAM Block LAB Row Interface
C4 and C8
Interconnects
Direct link
10
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
dataout
M512 RAM
Block
datain
Clocks
2
Control
Signals
address
8
Small RAM Block Local
Interconnect Region
LAB Row Clocks
R4 and R8
Interconnects
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K
RAM block implements buffers for a wide variety of applications such as
storing processor code, implementing lookup schemes, and
implementing larger memory applications. Each block contains
4,608 RAM bits (including parity bits). M4K RAM blocks can be
configured in the following modes:
■ True dual-port RAM
■ Simple dual-port RAM
■ Single-port RAM
■ FIFO
■ ROM
■ Shift register
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
4–26
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005