EP1SGX10DF672C6 Datasheet, PDF (225/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

DC & Switching Characteristics
Preliminary & Final Timing
Timing models can have either preliminary or final status. The
Quartus^® II software displays an informational message during the
design compilation if the timing models are preliminary. Table 6–34
shows the status of the Stratix GX device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
Table 6–34. Stratix GX Device Timing Model Status
Device
EP1SGX10
EP1SGX25
EP1SGX40
Preliminary
—
—
—
Final
v
v
v
Performance
Table 6–35 shows Stratix GX device performance for some common
designs. All performance values were obtained with Quartus II software
compilation of LPM, or MegaCore^® functions for the FIR and FFT
designs.
Table 6–35. Stratix GX Device Performance (Part 1 of 3) Notes (1), (2)
Resources Used
Performance
Applications
LE
16-to-1 multiplexer (1)
32-to-1 multiplexer (3)
16-bit counter
64-bit counter
LEs
TriMatrix
Memory
Blocks
DSP
Blocks
-5
Speed
Grade
-6
Speed
Grade
-7
Speed
Grade
22
0
46
0
16
0
64
0
0 407.83 324.56 288.68
0 318.26 255.29 242.89
0 422.11 422.11 390.01
0 321.85 290.52 261.23
Units
MHz
MHz
MHz
MHz
Altera Corporation
June 2006
6–23
Stratix GX Device Handbook, Volume 1