EP1SGX10DF672C6 Datasheet, PDF (150/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

PLLs & Clock Networks
Figure 4–52. Clock Switchover Circuitry
SMCLKSW
Clock
Sense
Switch-Over
State Machine
CLK0_BAD
CLK1_BAD
Active Clock
CLKLOSS
CLKSWITCH
CLK0
CLK1
Δt
MUXOUT
n Counter
PFD
FBCLK
Note to Figure 4–52:
(1) PFD: phase frequency detector.
Enhanced PLL
There are two possible ways to use the clock switchover feature.
■ You can use automatic switchover circuitry for switching between
inputs of the same frequency. For example, in applications that
require a redundant clock with the same frequency as the primary
clock, the switchover state machine generates a signal that controls
the multiplexer select input on the bottom of Figure 4–52. In this case,
the secondary clock becomes the reference clock for the PLL.
■ You can use the clkswitch input for user- or system-controlled
switch conditions. This is possible for same-frequency switchover or
to switch between inputs of different frequencies. For example, if
inclk0 is 66 MHz and inclk1 is 100 MHz, you must control the
switchover because the automatic clock-sense circuitry cannot
monitor primary and secondary clock frequencies with a frequency
difference of more than ±20%. This feature is useful when clock
sources can originate from multiple cards on the backplane,
4–84
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005