EP1SGX10DF672C6 Datasheet, PDF (153/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Altera Corporation
February 2005
Stratix GX Architecture
External Clock Outputs
Enhanced PLLs 5 and 6 each support up to eight single-ended clock
outputs (or four differential pairs). See Figure 4–54.
Figure 4–54. External Clock Outputs for PLLs 5 & 6
From IOE (1)
(2)
e0 Counter
extclk0_a
From IOE (1)
From IOE (1)
extclk0_b
extclk1_a
e1 Counter
4 ^{From IOE (1)}
From IOE (1)
extclk1_b
extclk2_a
e2 Counter
From IOE (1)
From IOE (1)
extclk2_b
extclk3_a
e3 Counter
From IOE (1)
extclk3_b
Notes to Figure 4–54:
(1) Each external clock output pin can be used as a general purpose output pin from
the logic array. These pins are multiplexed with IOE outputs.
(2) Two single-ended outputs are possible per output counter—either two outputs of
the same frequency and phase or one shifted 180°.
Any of the four external output counters can drive the single-ended or
differential clock outputs for PLLs 5 and 6. This means one counter or
frequency can drive all output pins available from PLL 5 or PLL 6. Each
4–87
Stratix GX Device Handbook, Volume 1