EP1SGX10DF672C6 Datasheet, PDF (155/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
Table 4–19. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2)
I/O Standard
SSTL-3 class I
SSTL-3 class II
AGP (1× and 2× )
CTT
INCLK
v
v
v
v
Input
FBIN
v
v
v
v
PLLENABLE
Output
EXTCLK
v
v
v
v
Enhanced PLLs 11 and 12 support one single-ended output each (see
Figure 4–55). These outputs do not have their own VCC and GND signals.
Therefore, to minimize jitter, do not place switching I/O pins next to this
output pin.
Figure 4–55. External Clock Outputs for Enhanced PLLs 11 & 12
g0
Counter
CLK13n, I/O, PLL11_OUT
or CLK6n, I/O, PLL12_OUT (1)
From Internal
Logic or IOE
Note to Figure 4–55:
(1) For PLL 11, this pin is CLK13n; for PLL 12 this pin is CLK7n.
Stratix GX devices can drive any enhanced PLL driven through the global
clock or regional clock network to any general I/O pin as an external
output clock. The jitter on the output clock is not guaranteed for these
cases.
Clock Feedback
The following four feedback modes in Stratix GX device enhanced PLLs
allow multiplication and/or phase and delay shifting:
■ Zero delay buffer: The external clock output pin is phase-aligned
with the clock input pin for zero delay.
■ External feedback: The external feedback input pin, FBIN, is
phase-aligned with the clock input, CLK, pin. Aligning these clocks
allows you to remove clock delay and skew between devices. This
mode is only possible for PLLs 5 and 6. PLLs 5 and 6 each support
Altera Corporation
February 2005
4–89
Stratix GX Device Handbook, Volume 1