EP1SGX10DF672C6 Datasheet, PDF (52/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Introduction
multiplication value. The ×1 and ×2 operation is also possible by
bypassing the SERDES. The SERDES DPA cannot support ×1, ×2, or ×4
natively.
On the receiver side, the high-frequency clock generated by the PLL shifts
the serial data through a shift register (also called deserializer). The
parallel data is clocked out to the logic array synchronized with the low-
frequency clock. On the transmitter side, the parallel data from the logic
array is first clocked into a parallel-in, serial-out shift register
synchronized with the low-frequency clock and then transmitted out by
the output buffers.
There are two dedicated fast PLLs each in EP1SGX10 to EP1SGX25
devices, and four in EP1SGX40 devices. These PLLs are used for the
SERDES operations as well as general-purpose use.
Stratix GX Differential I/O Receiver Operation (Non-DPA Mode)
You can configure any of the Stratix GX source synchronous differential
input channels as a receiver channel (see Figure 3–1). The differential
receiver deserializes the incoming high-speed data. The input shift
register continuously clocks the incoming data on the negative transition
of the high-frequency clock generated by the PLL clock (×W).
The data in the serial shift register is shifted into a parallel register by the
RXLOADEN signal generated by the fast PLL counter circuitry on the third
falling edge of the high-frequency clock. However, you can select which
falling edge of the high frequency clock loads the data into the parallel
register, using the data-realignment circuit.
In normal mode, the enable signal RXLOADEN loads the parallel data into
the next parallel register on the second rising edge of the low-frequency
clock. You can also load data to the parallel register through the
TXLOADEN signal when using the data-realignment circuit.
Figure 3–1 shows the block diagram of a single SERDES receiver channel.
Figure 3–2 shows the timing relationship between the data and clocks in
Stratix GX devices in ×10 mode. W is the low-frequency multiplier and J
is the data parallelization division factor.
3–2
Stratix GX Device Handbook, Volume 1
Altera Corporation
August 2005