EP1SGX10DF672C6 Datasheet, PDF (85/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
Table 4–2. TriMatrix Memory Features (Part 2 of 2)
Memory Feature
M512 RAM Block M4K RAM Block M-RAM Block
(32 × 18 Bits) (128 × 36 Bits) (4K × 144 Bits)
Configurations
512 ×1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
Notes to Table 4–2:
(1) See the DC & Switching Characteristics chapter of the Stratix GX Device Handbook,
Volume 1 for maximum performance information.
(2) The M-RAM block does not support memory initializations. However, the
M-RAM block can emulate a ROM function using a dual-port RAM bock. The
Stratix GX device must write to the dual-port memory once and then disable the
write-enable ports afterwards.
Memory Modes
TriMatrix memory blocks include input registers that synchronize writes
and output registers to pipeline designs and improve system
performance. M4K and M-RAM memory blocks offer a true dual-port
mode to support any combination of two-port operations: two reads, two
writes, or one read and one write at two different clock frequencies.
Figure 4–11 shows true dual-port memory.
Figure 4–11. True Dual-Port Memory Configuration
A
dataA[ ]
addressA[ ]
wrenA
clockA
clockenA
qA[ ]
aclrA
B
dataB[ ]
addressB[ ]
wrenB
clockB
clockenB
qB[ ]
aclrB
In addition to true dual-port memory, the memory blocks support simple
dual-port and single-port RAM. Simple dual-port memory supports a
simultaneous read and write and can either read old data before the write
Altera Corporation
February 2005
4–19
Stratix GX Device Handbook, Volume 1