EP1SGX10DF672C6 Datasheet, PDF (27/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Transceivers
Table 2–5. Receiver PLL & CRU Adjustable Parameters (Part 2 of 2)
Multiplication factor (W)
PPM detector
Bandwidth
Run length detector
2, 4, 5, 8, 10, 16, or 20 (1)
125, 250, 500, 1,000
Low, medium, high
10-bit or 20-bit mode: 5 to 160 in steps of
5
8-bit or 16-bit mode: 4 to 128 in steps of 4
Note to Table 2–5:
(1) Multiplication factors 2, 4, and 5 can only be achieved with the use of the pre-
divider on the REFCLKB port or if the CRU is trained with the low speed clock
from the transmitter PLL.
The CRU has a built-in switchover circuit to select whether the
voltage-controlled oscillator of the PLL is trained by the reference clock or
the data. The optional port rx_freqlocked monitors when the CRU is
in locked to data mode.
In the automatic mode, the following conditions must be met for the CRU
to switch from locked to reference to locked to data mode:
■ The CRU PLL is within the prescribed PPM frequency threshold
setting (125 PPM, 250 PPM, 500 PPM, 1,000 PPM) of the CRU
reference clock.
■ The reference clock and CRU PLL output are phase matched (phases
are within .08 UI).
The automatic switchover circuit can be overridden by using the optional
ports rx_lockedtorefclk and rx_locktodata. Table 2–6 shows the
possible combinations of these two signals.
Table 2–6. Possible Combinations of rx_lockedtorefclk & rx_locktodata
rx_locktodata
0
0
1
rx_lockedtorefclk
0
1
x
VCO (lock to mode)
Auto
Reference CLK
DATA
If the rx_lockedtorefclk and rx_locktodata ports are not used,
the default is auto mode.
Altera Corporation
June 2006
2–17
Stratix GX Device Handbook, Volume 1