EP1SGX10DF672C6 Datasheet, PDF (44/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Figure 2–29. EP1SGX25 Receiver PLL Recovered Clock to Fast Regional Clock
Connection
PLD
FCLK[1..0]
Stratix GX
Transceiver Blocks
Block 0
Block 1
Block 2
FCLK[1..0]
Block 3
In the EP1SGX40 device, the receiver PLL recovered clocks from
transceivers 0 and 1 drive RCLK[1..0] while transceivers 2, 3, and 4
drive RCLK[7..6]. The regional clocks feed logic in their associated
regions.
2–34
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006