EP1SGX10DF672C6 Datasheet, PDF (171/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Figure 4–65. Input Timing Diagram in DDR Mode
Data at
input pin
A0 B1 A1 B2 A2 B3 A3 B4
CLK
A'
Input To
Logic Array
B'
A1
A2
A3
B1
B2
B3
Stratix GX Architecture
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from LEs on rising clock edges. These
output registers are multiplexed by the clock to drive the output pin at a
×2 rate. One output register clocks the first bit out on the clock high time,
while the other output register clocks the second bit out on the clock low
time. Figure 4–66 shows the IOE configured for DDR output. Figure 4–67
shows the DDR output timing diagram.
Altera Corporation
February 2005
4–105
Stratix GX Device Handbook, Volume 1