EP1SGX10DF672C6 Datasheet, PDF (41/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Transceivers
Figure 2–26. EP1SGX25F Device Inter-Transceiver & Global Clock Connections Note (1)
Transceiver Block 0
IQ0
IQ1
Global Clocks, I/O Bus, General Routing
refclkb
/2
Transmitter
PLL
IQ2
IQ0
IQ1
IQ2
Global Clocks, I/O Bus, General Routing
4
4
Receiver
PLLs
Transceiver Block 1
IQ0
IQ1
Global Clocks, I/O Bus, General Routing
Transmitter
PLL
refclkb
/2
(2)
IQ2
Global Clocks, I/O Bus, General Routing
4
4
Receiver
PLLs
Transceiver Block 2
IQ0
IQ1
Global Clocks, I/O Bus, General Routing
Transmitter
PLL
refclkb
/2
(2)
IQ2
Global Clocks, I/O Bus, General Routing
4
4
Receiver
PLLs
16
PLD Global Clocks
Transceiver Block 3
IQ0
IQ1
Global Clocks, I/O Bus, General Routing
Transmitter
PLL
refclkb
/2
(2)
IQ2
Global Clocks, I/O Bus, General Routing
4
4
Receiver
PLLs
Notes to Figure 2–26:
(1) IQ lines are inter-transceiver block lines.
(2) If the /2 pre-divider is used, the path to drive the PLD logic array, local, or global clocks is not allowed.
(3) There are four receiver PLLs in each transceiver block.
Altera Corporation
June 2006
2–31
Stratix GX Device Handbook, Volume 1