EP1SGX10DF672C6 Datasheet, PDF (133/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
Figure 4–40. DSP Block Interface to Interconnect
C4 and C8
Interconnects
Direct Link Interconnect
from Adjacent LAB
R4 and R8 Interconnects
Nine Direct Link Outputs Direct Link Interconnect
to Adjacent LABs
from Adjacent LAB
LAB
10
18
DSP Block
Row Structure
LAB
9
9
10
3
Control
18
18
[17..0]
[17..0]
Row Interface
Block
DSP Block to
LAB Row Interface
Block Interconnect Region
18 Inputs per Row
18 Outputs per Row
A bus of 18 control signals feeds the entire DSP block. These signals
include clock[0..3] clocks, aclr[0..3] asynchronous clears,
ena[1..4] clock enables, signa, signb signed/unsigned control
signals, addnsub1 and addnsub3 addition and subtraction control
signals, and accum_sload[0..1] accumulator synchronous loads. The
Altera Corporation
February 2005
4–67
Stratix GX Device Handbook, Volume 1