EP1SGX10DF672C6 Datasheet, PDF (233/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

DC & Switching Characteristics
Figure 6–5. Stratix GX Transceiver Reset & PLL Lock Time Waveform Note (1)
rden
tWERESU
rdaddress
bn
b0
reg_data-out
doutn-2
doutn-1
unreg_data-out
doutn-1
doutn
tWEREH
t_RC
t_DATACO1
doutn
tDATACO2
Note to Figure 6–5:
(1) Waveforms are for minimum pulse width timing and output timing only. Please refer to the Stratix GX Transceiver
User Guide for the complete reset sequence.
Tables 6–44 through 6–50 show the internal timing microparameters for
all Stratix GX devices.
Table 6–44. LE Internal Timing Microparameters
Symbol
t_SU
t_H
t_CO
t_LUT
t_CLR
t_PRE
t_CLKHL
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Unit
Min Max Min Max Min Max
10
10
11
ps
100
100
114
ps
156
176
202
ps
366
459
527
ps
100
100
114
ps
100
100
114
ps
100
100
114
ps
Altera Corporation
June 2006
6–31
Stratix GX Device Handbook, Volume 1