EP1SGX10DF672C6 Datasheet, PDF (267/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

DC & Switching Characteristics
Table 6–90. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 3)
Symbol
t_FCOMP
f_OUT
f_{OUT_EXT}
t_OUTDUTY
t_JITTER
t_CONFIG5,6
t_CONFIG11,12
t_SCANCLK
t_DLOCK
t_LOCK
f_VCO
Parameter
Min Typ
External feedback clock compensation
time (3)
Output frequency for internal global or 0.3
regional clock
Output frequency for external clock (2) 0.3
Duty cycle for external clock output
45
(when set to 50%)
Period jitter for external clock output (5)
Time required to reconfigure the scan
chains for PLLs 5 and 6
Time required to reconfigure the scan
chains for PLLs 11 and 12
scanclk frequency (4)
Time required to lock dynamically (after (8)
switchover or reconfiguring any non-
post-scale counters/delays) (6) (10)
Time required to lock from end of
10
device configuration (10)
PLL internal VCO operating range
300
Max
6
420
434
55
±100 ps for >200 MHz outclk
±20 mUI for <200 MHz outclk
289/f_SCANCLK
193/f_SCANCLK
22
100
400
600 (7)
Unit
ns
MHz
MHz
%
ps or
mUI
MHz
μs
μs
MHz
Altera Corporation
June 2006
6–65
Stratix GX Device Handbook, Volume 1