EP1SGX10DF672C6 Datasheet, PDF (12/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Figure 2–1. Stratix GX Transceiver Block Note (1)
PLD
Logic
Array
Receiver Channel 0
Channel 0
Transmitter Channel 0
Receiver Pins
Transmitter Pins
PLD
Logic
Array
PLD
Logic
Array
Receiver Channel 1
Channel 1
Transmitter Channel 1
Receiver Pins
Transmitter Pins
XAUI
Receiver
State
Machine
XAUI
Transmitter
State
Machine
Channel
Aligner
State
Machine
Transmitter
PLL
PLD
Logic
Array
(2)
PLD
Logic
Array
Receiver Channel 2
Channel 2
Transmitter Channel 2
Receiver Pins
Transmitter Pins
PLD
Logic
Array
Receiver Channel 3
Channel 3
Transmitter Channel 3
Receiver Pins
Transmitter Pins
Notes to Figure 2–1:
(1) Each receiver channel has its own PLL and CRU, which are not shown in this diagram. For more information, refer
to the section “Receiver Path” on page 2–13.
(2) For possible transmitter PLL clock inputs, refer to the section “Transmitter Path” on page 2–5.
2–2
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006