EP1SGX10DF672C6 Datasheet, PDF (261/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

DC & Switching Characteristics
Table 6–86. High-Speed Timing Specifications & Definitions (Part 2 of 2)
High-Speed Timing Specification
t_FALL
Timing unit interval (TUI)
f_HSDR
f_HSDRDPA
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak)
Output jitter (peak-to-peak)
t_DUTY
t_LOCK
Definitions
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t_C/w).
Maximum/minimum LVDS data transfer rate (f_HSDR = 1/TUI), non-DPA.
Maximum/minimum LVDS data transfer rate (f_HSDRDPA = 1/TUI), DPA.
The timing difference between the fastest and slowest output edges,
including t_CO variation and clock skew. The clock is included in the TCCS
measurement.
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
SW = t_SW (max) – t_SW (min).
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
Table 6–87 shows the high-speed I/O timing specifications for Stratix GX
devices.
Table 6–87. High-Speed I/O Specifications (Part 1 of 4) Notes (1), (2)
Symbol
Conditions
f_HSCLK (Clock
frequency)
(LVDS,
LVPECL,
HyperTransport
technology)
f_HSCLK =
f_HSDR / W
W = 1 to 30 for ≤717
Mbps
W = 2 to 30 for > 717
Mbps
f_{HSCLK_DPA}
-5 Speed Grade
Min Typ Max
10
717
-6 Speed Grade
Min Typ Max
10
717
-7 Speed Grade
Unit
Min Typ Max
10
624 MHz
74
717 74
717 74
717 MHz
Altera Corporation
June 2006
6–59
Stratix GX Device Handbook, Volume 1