EP1SGX10DF672C6 Datasheet, PDF (80/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

MultiTrack Interconnect
Figure 4–9. LUT Chain & Register Chain Interconnects
Local Interconnect
Routing Among LEs
in the LAB
LUT Chain
Routing to
Adjacent LE
Local
Interconnect
LE 1
LE 2
LE 3
LE 4
Register Chain
Routing to Adjacent
LE's Register Input
LE 5
LE 6
LE 7
LE 8
LE 9
LE 10
The C4 interconnects span four LABs, M512, or M4K blocks up or down
from a source LAB. Every LAB has its own set of C4 interconnects to drive
either up or down. Figure 4–10 shows the C4 interconnect connections
from an LAB in a column. The C4 interconnects can drive and be driven
by all types of architecture blocks, including DSP blocks, TriMatrix
memory blocks, and vertical IOEs. For LAB interconnection, a primary
LAB or its LAB neighbor can drive a given C4 interconnect.
C4 interconnects can drive each other to extend their range as well as
drive row interconnects for column-to-column connections.
4–14
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005