EP1SGX10DF672C6 Datasheet, PDF (136/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

PLLs & Clock Networks
Figure 4–41. Global Clock Resources
CLK[15..12]
CLK[3..0]
Global Clock [15..0]
Transceiver
Clocks
CLK[7..4]
Regional Clock Network
There are four regional clock networks RCLK[3..0] within each
quadrant of the Stratix GX device that are driven by the same dedicated
CLK[7..0] and CLK[15..12] input pins, PLL outputs, or transceiver
clocks. The regional clock networks only pertain to the quadrant they
drive into. The regional clock networks provide the lowest clock delay
and skew for logic contained within a single quadrant. The CLK clock pins
symmetrically drive the RCLK networks within a particular quadrant, as
shown in Figure 4–42.
4–70
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005