EP1SGX10DF672C6 Datasheet, PDF (79/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Stratix GX Architecture
LAB and do not drive directly to LAB local interconnects. R24 row
interconnects drive LAB local interconnects via R4 and C4 interconnects.
R24 interconnects can drive R24, R4, C16, and C4 interconnects.
The column interconnect operates similarly to the row interconnect and
vertically routes signals to and from LABs, TriMatrix memory, DSP
blocks, and IOEs. Each column of LABs is served by a dedicated column
interconnect, which vertically routes signals to and from LABs, TriMatrix
memory and DSP blocks, and horizontal IOEs. These column resources
include:
■ LUT chain interconnects within an LAB
■ Register chain interconnects within an LAB
■ C4 interconnects traversing a distance of four blocks in up and down
direction
■ C8 interconnects traversing a distance of eight blocks in up and
down direction
■ C16 column interconnects for high-speed vertical routing through
the device
Stratix GX devices include an enhanced interconnect structure within
LABs for routing LE output to LE input connections faster using LUT
chain connections and register chain connections. The LUT chain
connection allows the combinatorial output of an LE to directly drive the
fast input of the LE right below it, bypassing the local interconnect. These
resources can be used as a high-speed connection for wide fan-in
functions from LE 1 to LE 10 in the same LAB. The register chain
connection allows the register output of one LE to connect directly to the
register input of the next LE in the LAB for fast shift registers. The
Quartus II Compiler automatically takes advantage of these resources to
improve utilization and performance. Figure 4–9 shows the LUT chain
and register chain interconnects.
Altera Corporation
February 2005
4–13
Stratix GX Device Handbook, Volume 1