EP1SGX10DF672C6 Datasheet, PDF (54/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Introduction
The logic array sends parallel data to the SERDES transmitter circuit
when the TXLOADEN signal is asserted. This signal is generated by the
high-speed counter circuitry of the logic array low-frequency clock’s
rising edge. The data is then transferred from the parallel register into the
serial shift register by the TXLOADEN signal on the third rising edge of the
high-frequency clock.
Figure 3–3 shows the block diagram of a single SERDES transmitter
channel and Figure 3–4 shows the timing relationship between the data
and clocks in Stratix GX devices in ×10 mode. W is the low-frequency
multiplier and J is the data parallelization division factor.
Figure 3–3. Stratix GX High-Speed Interface Serialized in ×10 Mode
Stratix GX
Logic Array
Transmitter Circuit
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Parallel
Register
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Serial
Register
TXOUT+
TXOUT−
×W
Fast
PLL
TXLOADEN
Figure 3–4. Transmitter Timing Diagram
Internal ×1 clock
Internal ×10 clock
TXLOADEN
Receiver
data input
n–1 n–0 9
8
7
6
5
4
3
2
1
0
3–4
Stratix GX Device Handbook, Volume 1
Altera Corporation
August 2005