EP1SGX10DF672C6 Datasheet, PDF (59/272 Pages) Altera Corporation – Section I. Stratix GX Device Family Data Sheet

Source-Synchronous Signaling With DPA
Figure 3–7. PLL & Channel Layout in EP1SGX40 Devices Notes (1), (2), (3)
CLKIN
PLL (1)
1 Receiver
1 Transmitter
22 Rows
1 Transmitter
1 Receiver
INCLK0
INCLK1
1 Receiver
1 Transmitter
23 Rows
8
Fast
PLL 1
Fast
PLL 2
Eight-Phase
Clock
Eight-Phase
Clock
8
1 Transmitter
1 Receiver
CLKIN
PLL (1)
Notes to Figure 3–7:
(1) Corner PLLs do not support DPA.
(2) Not all eight phases are used by the receiver channel or transmitter channel in
non-DPA mode.
(3) The center PLLs can only clock 20 transceivers in either direction. Using Fast PLL2,
you can clock a total of 40 transceivers, 20 in each direction.
Altera Corporation
August 2005
3–9
Stratix GX Device Handbook, Volume 1