PD17012_15 Datasheet, PDF (87/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
10.3.4 Using I/O ports (P0A, P0B, P1A, and P1D) as input ports
Select the pin to be used as an input port pin by the I/O select register corresponding to each port.
Note that P1D can be set in the input or output mode in 4-bit units only.
The pin specified as an input port pin is floated (Hi-Z), and waits for input of an external signal.
The input data can be read by executing an instruction that reads the contents of the port register
corresponding to each port, such as the SKT instruction.
When a high level is input to each pin, 1 is read to the corresponding port register; when a low level is input,
0 is read.
If a write instruction, such as MOV, is executed to the port register corresponding to the port pin specified
as an input port pin, the contents of the output latch are rewritten.
10.3.5 Using I/O ports (P0A, P0B, P1A, and P1D) as output ports
Select the pin to be used as an output port pin by the I/O select register corresponding to each port.
Note that P1D can be set in the input or output mode in 4-bit units only.
The pin specified as an output port pin outputs the contents of the output latch.
The output data can be set by executing an instruction that writes the contents of the corresponding port
register to each pin, such as the MOV instruction.
To output a high level to each pin, write 1 to the corresponding port register; to output a low level, write 0.
The port pin can also be floated when it is specified as an input port pin.
When an instruction, such as SKT, that reads the contents of the port register corresponding to a port
specified as an output port is executed, the contents of the output latch are read.
10.3.6 Status of I/O ports (P0A, P0B, P1A, and P1D) on reset
(1) On power-on reset
All the I/O ports are set in the input mode.
Because the contents of the output latch are undefined, the output latch must be initialized by program, as
necessary, before setting the corresponding port in the output mode.
(2) On CE reset
All the I/O ports are set in the input mode.
The contents of the output latch are retained.
(3) On execution of clock stop instruction
All the I/O ports are set in the input mode.
The contents of the output latch are retained.
I/O ports other than P1D prevent an increase in the current consumption due to the noise of the input buffer
by using the RESET signal when the clock stop instruction is executed, as explained in 10.3.1.
If P1D is floated on execution of the clock stop instruction, the current consumption may increase due to
external noise. Externally pull this port down or up as necessary.
(4) In halt status
The previous status is retained.
Data Sheet U10101EJ4V0DS
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