PD17012_15 Datasheet, PDF (183/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
16.3 Input Select Block and Programmable Divider
16.3.1 Configuration of input select block and programmable divider
Figure 16-2 shows the configuration of the input select block and programmable divider.
As shown in the figure, the input select block consists of the VCOH and VCOL pins, and the amplifiers of the
respective pins.
The programmable divider consists of a 2-modulus prescaler, swallow counter, programmable counter, and
division mode select switch.
Figure 16-2. Configuration of Input Select Block and Programmable Divider
Control register
Address
21H
Bit
b3 b2 b1 b0
Flag
symbol
0 0PP
LL
LL
MM
DD
10
2-4 decoder
Data buffer (DBF)
Address 0CH
0DH
0EH
Symbol DBF3 DBF2 DBF1
Data
M
S
B
0FH
DBF0
L
S
B
16
Peripheral address 41H
PLL data register
12 bits
4 bits
VCOH
VHF
MF
VHF
HF
PSC
2-modulus
prescaler
1/16, 1/17
VHF
HF
MF
12
4
Swallow
counter 4 bits
Programmable
counter 12 bits
fN
To φ -DET
VCOL
MF
HF
PLL disable signal
Data Sheet U10101EJ4V0DS
181