PD17012_15 Datasheet, PDF (189/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
16.4.2 Configuration and function of PLL reference clock select register
The configuration and function of the PLL reference clock select register are shown below.
Name
PLL reference clock
select register
Flag symbol Address
b3 b2 b1 b0
PPPP
31H
LLLL
LLLL
RRRR
FFFF
CCCC
KKKK
3210
Read/
write
R/W
Sets reference frequency fr of PLL frequency synthesizer
0 0 0 0 1.25 kHz
0 0 0 1 2.5 kHz
0 0 1 0 5 kHz
0 0 1 1 10 kHz
0 1 0 0 6.25 kHz
0 1 0 1 12.5 kHz
0 1 1 0 25 kHz
0 1 1 1 50 kHz
1 0 0 0 3 kHz
1 0 0 1 Setting prohibited
1 0 1 0 Setting prohibited
1 0 1 1 Setting prohibited
1 1 0 0 1 kHz
1 1 0 1 9 kHz
1 1 1 0 100 kHz
1 1 1 1 PLL disabled
Power-on
Clock stop
CE
1111
1111
Retained
When the PLL is disabled by the PLL reference clock select register, the VCOH and VCOL pins are internally
pulled down.
The EO pin is floated.
For disabling the PLL, refer to 16.6.
Data Sheet U10101EJ4V0DS
187