PD17012_15 Datasheet, PDF (272/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
22.2 Reset Function
Power-on reset is effected when supply voltage VDD rises from a specific level, and CE reset is effected when
the CE pin goes high.
Power-on reset initializes the program counter, stack, system register, and control registers, and executes
the program from address 0000H.
CE reset initializes the program counter, stack, system register, and some control registers, and executes
the program from address 0000H.
The major differences between power-on reset and CE reset are the control registers that are initialized and
the operation of the power failure detector that is explained in 22.6.
Both power-on reset and CE reset are controlled by the reset signals IRES, RES, and RESET output from
the reset controller shown in Figure 22-1.
Table 22-1 shows the relationship between the IRES, RES, and RESET signals, and power-on reset, and CE
reset.
The reset controller also operates when the clock stop instruction (STOP s) explained in 21. STANDBY is
executed.
The following sections 22.3 and 22.4 explain CE reset and power-on reset respectively.
Section 22.5 explains the relationship between CE reset and power-on reset.
Table 22-1. Relationship Between Internal Reset Signals and Each Reset Operation
Internal Reset Signal
IRES
RES
RESET
CE Reset
×
×
Output Signal
Power-on
Reset
Clock Stop
Control Operation by Each Reset Signal
Forcibly sets device in halt status.
Halt status is released when basic timer 0 carry
FF is set.
Initializes some control registers.
Initializes program counter, stack, system
register, and some control registers.
270
Data Sheet U10101EJ4V0DS