PD17012_15 Datasheet, PDF (47/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
5.6 Index Register (IX) and Data Memory Row Address Pointer (MP: Memory Pointer)
5.6.1 Configuration of index register and data memory row address pointer
Figure 5-6 shows the configuration of the index register and data memory row address pointer.
As shown in the figure, the index register consists of an index register (IX) and an index enable flag (IXE).
IX is an 11-bit register consisting of the lower 3 bits (IXH) of system register address 7AH, and addresses 7BH
and 7CH (IXM and IXL). IXE is the least significant bit of address 7FH (PSW).
The data memory row address pointer (memory pointer) consists of a data memory row address pointer, which
consists of 7 bits with the lower 3 bits of address 7AH (MPH) and address 7BH (MPL), and a data memory row
address pointer enable flag (memory pointer enable flag: MPE), which is the most significant bit of address 7AH
(MPH).
In other words, the higher 7 bits of the index register are shared with the data memory row address pointer.
Note, however, that the higher 2 bits of the index register and data memory row address pointer (bits b2 and
b1 of address 7AH) are always fixed to 0.
Figure 5-6. Configuration of Index Register and Data Memory Row Address Pointer
Address
Name
Symbol
Bit
Data
7AH
7BH
7CH
7EH
7FH
Index register (IX)
Program status word
Memory pointer (MP)
(PSWORD)
IXH
IXM
IXL
PSW
MPH
MPL
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0
M0 0 M
L
I
P
S
S
X
E
B
B
E
IX
M
L
S
S
B
B
MP
Power-on
0
0
0
0
Clock stop
0
0
0
0
CE
0
0
0
0
Data Sheet U10101EJ4V0DS
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