PD17012_15 Datasheet, PDF (177/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
15.7 Wait Control Block
The wait control block controls communication of the serial interface by placing or releasing communication
in or from the wait status.
The wait control block is controlled by the SIO1TS flag of the serial I/O mode select register.
The following subsection 15.7.1 explains the wait operation and points to be noted.
15.7.1 Wait operation and notes
In the wait status, the clock generation block and presettable shift register stop operation, and serial
communication pauses.
Therefore, serial communication can be started when the wait status is released.
The wait status is released when 1 is written to the SIO1TS flag.
When 1 is written to this flag, the internal clock is output to the shift clock output pin (during master operation),
and presettable shift register and clock counter start operating.
If the shift clock rises when the value of the clock counter is 8, the wait status is set. At this time, the SIO1TS
flag is automatically reset to 0.
The operating status of serial communication can be checked by detecting the content of the SIO1TS flag
while the wait status is released.
Therefore, data is read or set after 1 has been written to the SIO1TS flag, serial communication has been
started, and then clearing of the SIO1TS flag to 0 has been detected.
If data is written to (by PUT instruction) or read from (by GET instruction) the presettable shift register while
the wait status is released, the correct data may not be written or read.
For details, refer to 15.6.2 Notes on setting and reading data.
If 0 is written to the SIO1TS flag while the wait status is released, the wait status is set. This is called forced
wait. When forced wait is executed, the clock counter is reset to 0.
Figure 15-4 shows an example of the wait operation.
Data Sheet U10101EJ4V0DS
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