PD17012_15 Datasheet, PDF (226/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
19.6 Output Waveforms of Common and Segment Signals
Figures 19-10 to 19-12 show the output waveforms of the common and segment signals.
Figure 19-10 shows the output waveform with the key source signals not output, and Figures 19-11 and 19-
12 show the output waveform with the key source signals output.
As shown in Figure 19-10, the LCD driver outputs signals with a frame frequency of 83 Hz at 1/3 duty, 1/2
bias (voltage average mode).
As the common signals, three levels of voltages (GND, 1/2 VDD, and VDD) each having a phase difference
of 1/6 from the others are output from the COM1 and COM0 pins.
Therefore, voltages in a range of 1/2VDD ± 1/2 VDD are output. This display mode is called 1/2 bias drive mode.
As the segment signals, two levels (0, VDD) of voltages each having a phase corresponding to a display dot
are output from each segment signal output pin.
Because three display dots (A, B, and C) are turned on/off by one segment pin as shown in Figure 19-10,
eight types of phases <1> through <8> shown in Figure 19-10 are output by combination of each dot, and on
and off.
Each display dot is turned on when the potential difference between the common and segment signals
reaches VDD.
The duty factor at which each display dot is turned on is 1/3, and the frequency of the LCD clock is
167 Hz.
This display mode is called 1/3 duty drive mode.
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Data Sheet U10101EJ4V0DS