PD17012_15 Datasheet, PDF (148/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
13.3 Compare Voltage Generator Block and Compare Block
Figure 13-4 shows the configuration of the compare voltage generator block and compare block.
The compare voltage generator block switches over the tap decoder by using 6-bit data set to the A/D converter
data register to generate 64 steps of compare voltage VREF.
In other words, this block is an R-string D/A converter.
The power source of the R string is the same as the VDD supplied to the device.
The voltage applied to the resistor of the R string is only supplied when the ADCCMP flag is read by using the PEEK
instruction.
The compare block judges which of the voltage VADCIN input from a pin and compare voltage VREF is greater.
Comparison is made by a comparator when the ADCCMP flag is read. Therefore, one compare time of the A/D
converter is equal to one instruction execution time (4.44 µs).
Figures 13-5 and 13-6 show the configuration and function of the A/D converter compare judge register and A/
D converter data register. Table 13-1 lists the compare voltages.
Figure 13-4. Configuration of Compare Voltage Generator Block and Compare Block
1/2 VDD
DBF
VADCIN
VREF
A/D converter data
register (ADCR)
Tap decoder
0
1
2 62
63
1
2R ^R
3
R
2R
2 pF
−
Comparator
+
ADCCMP
flag
VDD
Reading ADCCMP flag
by PEEK instruction
146
Data Sheet U10101EJ4V0DS