PD17012_15 Datasheet, PDF (237/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
20.4 Output Timing Control Blocks and Segment/Port Select Block
20.4.1 Configuration of output timing control blocks and segment/port select block
Figure 20-4 shows the configuration of the common signal and segment signal/key source signal output timing
control blocks and segment signal/general-purpose output port select block.
Figure 20-4. Configuration of Timing Control Blocks and Port Select Block
LCDEN flag KSEN flag
LCD15/KS15/PYA15
|
LCD0/KS0/PYA0
PYASEL flag
Basic clock for
timing control
Port data
1
0
Segment signal/
key source signal
Segment signal/
key source
signal timing
control
Key source data register/
port YA group register
b0
LCDD15
b1
|
LCDD0
b2
To key input control block and KEYJ flag
20.4.2 Function of output timing control block
The segment signal/key source signal output timing control block controls the output timing of the key source
and segment signals.
The LCD segment signal is output when the LCDEN flag of the LCD mode select register is 1.
All the LCD display dots can be turned off by resetting the LCDEN flag to 0. At this time, a low level is output
as the segment signal, and the key source signal is not output.
To output the key source signal, therefore, the LCDEN flag must be 1.
The key source signal is also output when the KSEN flag of the LCD mode select register is 1.
Therefore, the KSEN flag is used to specify whether the key source signal is used or not.
To output the key source signal, therefore, the LCDEN and KSEN flags must be 1.
The following subsection 20.4.3 indicates the configuration and function of the LCD mode select register.
Subsection 20.4.4 shows the output waveforms of the key source and segment signals.
For the relationship between the common and segment signals of the LCD, and key source signal, refer to
19. LCD CONTROLLER/DRIVER.
Data Sheet U10101EJ4V0DS
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