PD17012_15 Datasheet, PDF (172/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
15.4 Clock Generation Block
The clock generation block generates the clock when the internal clock is used (i.e., when a master operation
is performed) and controls the clock output timing.
The frequency fSC of the internal clock is set by using the SIO1CK1 and SIO1CK0 flags of the serial I/O mode
select register.
The shift clock is successively output until the value of the clock counter, which is explained in 15.5, reaches
“8”.
The following subsection 15.4.1 explains the clock output waveform and clock generation timing.
15.4.1 Internal shift clock generation timing
(1) On releasing wait status from initial status
The initial status is the status in which the internal clock is selected and the P0A2/SCK1 pin is set in the output
mode.
A high level is output to the P0A2/SCK1 pin in the wait status.
Wait release and clock selection can be made simultaneously.
Shift clock
1:1
Wait status
Initialization
1/fSC
Wait release
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Data Sheet U10101EJ4V0DS