PD17012_15 Datasheet, PDF (163/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
14.4.3 Function and operation of duty setting blocks
The duty setting blocks compare the value set to each PWM data register (PWM1 and PWM0) with the value
of each basic clock (fPWM1 and fPWM0) counted by an 8-bit counter, and output a high level if the value of the PWM
data register is greater, and a low level if the value of PWM data register is less.
Where the value set to the PWM data register is “x”, the duty factor is as follows.
x + 0.25
Duty factor: D =
× 100%
256
0.25 is an offset. A high level is output even when x = 0.
Because the basic clock is 1.125 MHz, the frequency and cycle of the output signal are as follows.
1.125 MHz
Frequency: f =
= 4.3945 kHz
256
Cycle:
256
T=
= 227.6 µs
1.125 MHz
An independent value can be set to each PWM data register via the data buffer.
In other words, each pin can output a signal with an independent duty factor.
The following subsections 14.4.4 and 14.4.5 explain the configuration and function of each PWM data
register, and the relationship between the output waveform and duty factor of each pin.
Data Sheet U10101EJ4V0DS
161