PD17012_15 Datasheet, PDF (185/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
16.3.3 Configuration and function of PLL mode select register
The PLL mode select register specifies the division mode of the PLL frequency synthesizer and the pin to
be used.
The configuration and function of the PLL mode select register are shown below.
The paragraphs (1) through (4) below outline the respective division modes.
Name
Flag symbol Address
b3 b2 b1 b0
PLL mode select register 0 0 P P 21H
LL
LL
MM
DD
10
Read/
write
R/W
Sets division mode of PLL frequency synthesizer
0 0 Disables VCOL and VCOH pins
0 1 Direct division mode (VCOL pin, MF mode)
1 0 Pulse swallow (VCOH pin, VHF mode)
1 1 Pulse swallow (VCOL pin, HF mode)
Fixed to “0”
Power-on
Clock stop
CE
0000
00
Retained
(1) Direct division mode (MF)
In this mode, the VCOL pin is used.
The VCOH pin is pulled down.
In the direct division mode, the frequency of the input signal is divided only by the programmable counter.
(2) Pulse swallow mode (HF)
The VOL pin is used in this mode.
The VCOH pin is pulled down.
In this mode, the frequency of the input signal is divided by the swallow counter and programmable counter.
(3) Pulse swallow mode (VHF)
The VCOH pin is used in this mode.
The VCOL pin is pulled down.
In this mode, the frequency of the input signal is divided by the swallow counter and programmable counter.
(4) Disabling VCOL and VCOH pins
The VCOH and VCOL pins are internally pulled down.
However, the phase comparator, reference frequency generator, and charge pump operate.
Therefore, the operation is different from that in the PLL disable status to be explained later.
Data Sheet U10101EJ4V0DS
183