PD17012_15 Datasheet, PDF (257/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
21.4.2 Halt release condition
Figure 21-3 shows the halt release conditions.
As shown in this figure, the halt release conditions are set by 4-bit data specified by operand “h” of the HALT
h instruction.
The halt status is released when the condition specified as “1” by operand “h” is satisfied.
When the halt status is released, the execution starts from the instruction next to the HALT h instruction.
If two or more release conditions are specified, and if any one of the specified conditions is satisfied, the halt
condition is released.
If the device is reset (power-on reset or CE reset), the halt status is released, and each reset operation is
performed.
If 0000B is set as the halt release condition “h”, no release condition is set.
At this time, the halt status is released if the device is reset (power-on reset or CE reset).
The following subsections 21.4.3 through 21.4.5 explains halt release conditions set by key input, basic timer
0, and interrupt.
21.4.6 shows an example when two or more release conditions are specified.
Figure 21-3. Halt Release Condition
HALT h (4 bits)
Operand bit
b3 b2 b1 b0
Sets halt release condition
Releases if high level is input to P0D pin (P0D3/K3 to P0D0/K0)
Releases if basic timer 0 carry FF is set to 1
Undefined (fixed to 0)
Releases if interrupt (INT pin or timer) is acknowledged
0
Does not release even if condition is satisfied
1
Releases if condition is satisfied
Data Sheet U10101EJ4V0DS
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