PD17012_15 Datasheet, PDF (188/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
16.4 Reference Frequency Generator
16.4.1 Configuration and function of reference frequency generator
Figure 16-3 shows the configuration of the reference frequency generator.
As shown in the figure, the reference frequency generator divides the crystal oscillator’s 4.5 MHz to generate
the reference frequency “fr” of the PLL frequency synthesizer.
Twelve reference frequencies can be selected: 1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25, 50, and 100 kHz.
Reference frequency fr is selected by the PLL reference clock select register.
16.4.2 shows the configuration and function of the PLL reference clock select register.
Figure 16-3. Configuration of Reference Frequency Generator (RFG)
4.5 MHz
Divider
Control register
Address
31H
Bit
b3 b2 b1 b0
Flag
symbol
P PPP
L LLL
L LLL
R RRR
F FFF
C CCC
K KKK
3 210
4-16 decoder
1 kHz
1.25 kHz
2.5 kHz
50 kHz
100 kHz
MUX
PLL disable signal
To φ -DET
186
Data Sheet U10101EJ4V0DS