PD17012_15 Datasheet, PDF (123/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
Therefore, as shown in Figure 12-7, the error of the time until the BTM0CY flag is first set after the
BTM0CY flag setting time has been changed is as follows:
–tSET < Error < tCHECK
tSET: New setting time of BTM0CY flag
tCHECK: Time to detect BTM0CY flag
Phase differences are provided among the internal pules of 4, 10, 200 Hz, and 1 kHz. Because these
phase differences are shorter than the newly set pulse time, they are included in the above error.
For the phase difference of each pulse, refer to 12.3.5 Notes on using basic timer 1.
Figure 12-7. Timer Error When BTM0CY Flag Setting Time Is Changed from A to B
(a) −tSET difference
(b) tCHECK difference
H
Internal pulse A
L
H
Internal pulse B
L
tSET
BTM0CY flag ^H
setting pulse
L
BTM0CY flag
H
L
a ^.=. 0
a
SKT1 BTM0CY
Intrinsic timer time
Actual timer time
Time changed
An error of -tSET occurs if the BTM0CY flag
is detected immediately after the timer time
has been changed because the flag then
becomes “1”.
tSET
a ^.=. 0
a
tCHECK
Intrinsic timer time
Actual timer time
Time changed
An error of tCHECK occurs if the timer time is
changed immediately after the BTM0CY
flag has been detected because the flag is
then reset once.
Data Sheet U10101EJ4V0DS
121