PD17012_15 Datasheet, PDF (243/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
Figure 20-9. Timing Chart of Key Source Signal, Key Input Signal, and Key Input Data (P0D port register)
H
Segment pin
L
<1> When P0D port register is “1”
H
Key input pin input signal
L
1
P0D port register
0
<2> When P0D port register is “0”
H
Key input pin input signal
L
1
P0D port register
0
The KEYJ flag is “0” during this period. If the value
of P0D is read, the status of the P0D pin is read.
Input data is latched at this point.
20.5.3 Configuration and function of key input judge register
The key input judge register detects the presence or absence of the key input signal latch when the LCD
segment signal output pins are shared with key source signal output.
The configuration and functions of this register are illustrated below.
Name
Key input judge register
Flag symbol _Address
b3 b2 b1 b0
Read/
write
000K
E
Y
J
16H R & Reset
Power-on
Clock stop
CE
Detects valid/invalid latch contents of key input signal
0 Invalid key latch contents
1 Valid latch contents
Fixed to 0
0000
0
0
Caution The KEYJ flag is not set to 1 when in HALT mode.
The KEYJ flag retains the data prior to HALT instruction execution.
Data Sheet U10101EJ4V0DS
241