PD17012_15 Datasheet, PDF (112/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
11.7 Operations After Acknowledging Interrupt
When an interrupt has been acknowledged, the following processing is sequentially executed.
(1) The interrupt enable flip-flop and the interrupt request flag corresponding to the acknowledged interrupt are
reset to 0, disabling the interrupts.
(2) The contents of the stack pointer are decremented by one.
(3) The contents of the program counter are saved to the address stack register specified by the stack pointer.
The contents saved at this time are the next program memory address that is used after the interrupt has been
acknowledged. For example, if a branch instruction is executed, the contents saved are the branch destination
address; if a subroutine call instruction is executed, they are the called address. Because the interrupt is
acknowledged after the next instruction is executed as a NOP instruction if a skip condition is satisfied by a
skip instruction, the saved contents are the skipped address.
(4) The lower 2 bits of the bank register (BANK), lower 5 bits of the general register pointer (RP), and 5 bits of
the program status word (PSWORD) are saved to the interrupt stack.
(5) The contents of the vector address generator corresponding to the acknowledged interrupt are transferred
to the program counter. In other words, execution branches to an interrupt servicing routine.
The processing (1) through (5) above is executed in one special instruction cycle (4.44 µs) in which the normal
instruction is not executed. This instruction cycle is called an interrupt cycle.
In other words, one instruction cycle time is necessary since an interrupt has been acknowledged until
execution branches to the corresponding vector address.
11.8 Restoring from Interrupt Servicing Routine
To restore execution from an interrupt servicing routine to the processing that was being performed when
the interrupt occurred, a dedicated instruction, “RETI”, is used.
When the RETI instruction is executed, the following processing is sequentially executed.
(1) The contents of the address stack register specified by the stack pointer are saved to the program counter.
(2) The contents of the interrupt stack are restored to the lower 2 bits of the bank register (BANK), lower 5 bits
of the general register pointer (RP), and 5 bits of the program status word (PSWORD).
(3) The contents of the stack pointer are incremented by one.
The processing (1) through (3) above is executed in one instruction cycle in which the RETI instruction is
executed.
The difference between the RETI instruction and subroutine return instructions “RET” and “RETSK” is only
the restoring operation of the system register in (2) above.
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Data Sheet U10101EJ4V0DS