PD17012_15 Datasheet, PDF (214/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
18.3 Clock Select Block and Clock Generator Block
The clock select block selects the output frequencies of the BEEP1 and BEEP0 pins by using the BEEP clock select
register.
The clock generator block generates the clock to be output to the BEEP1 and BEEP0 pins.
The clock frequency to be generated is 1 kHz, 3 kHz, 200 Hz, or 9 kHz.
Figure 18-4 shows the configuration and function of the BEEP clock select register.
Figure 18-4. Configuration of BEEP Clock Select Register
Name
BEEP clock select
register
Flag symbol Address
b3 b2 b1 b0
B B B B 25H
EEE E
EEE E
PPP P
110 0
CCC C
KKK K
101 0
Read/
write
R/W
0 0 1 kHz
0 1 3 kHz
1 0 200 Hz
1 1 9 kHz
Sets output frequency of BEEP0
00
01
10
11
1 kHz
3 kHz
200 Hz
9 kHz
Sets output frequency of BEEP1
Power-on
Clock stop
CE
0000
0000
Retained
212
Data Sheet U10101EJ4V0DS