PD17012_15 Datasheet, PDF (162/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
14.4 Duty Setting Blocks and Clock Generation Block
14.4.1 Configuration of duty setting blocks and clock generation block
Figure 14-4 shows the configuration of the duty setting blocks and clock generation block.
Figure 14-4. Configuration of Duty Setting Blocks and Clock Generation Block
Address
Symbol
Data
Data buffer (DBF)
0CH
0DH
0EH
DBF3
DBF2
DBF1
Don't care Don't care ^M
S
B
0FH
DBF0
L
S
B
To output block
To output block
Peripheral address 05H
8
PWM1 data register
(PWMR1)
Comparator
Counter (8 bits)
Peripheral address 04H
8
PWM0 data register
(PWMR0)
Comparator
Counter (8 bits)
fPWM1
1.125 MHz
Clock
generation
block
fPWM0
1.125 MHz
14.4.2 Function and configuration of clock generation blocks
The clock generation block outputs the basic clocks (fPWM1 and fPWM0) that set the duty factor of each output
signal (of PWM1 and PWM0 pins).
The output frequency is 1.125 MHz (0.89 µs) for both fPWM1 and fPWM0.
However, fPWM1 and fPWM0 have the following phase difference.
fPWM1
fPWM0
222 ns
222 ns
888 ns
160
Data Sheet U10101EJ4V0DS