PD17012_15 Datasheet, PDF (31/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
2.4 Program Flow
The execution flow of the program is controlled by the program counter, which specifies an address of the
program memory.
Figure 2-4 shows the value set to the program counter when each instruction is executed.
Table 2-1 shows the vector address when an interrupt is acknowledged.
2.4.1 Branch instructions
(1) Direct branch (“BR addr”)
The branch destination address of the direct branch instruction is in the area of addresses 0000H to
0FFFH, i.e. all the addresses of the program memory.
(2) Indirect branch (“BR @AR”)
The branch destination address of the indirect branch instruction is in the area of addresses 0000H to
0FFFH, i.e. all the addresses of the program memory.
Also refer to 5.3 Address Register (AR).
2.4.2 Subroutine
(1) Direct subroutine call (“CALL addr”)
The top address of the subroutine that can be called by the direct subroutine call instruction is within page
0 (addresses 0000H to 07FFH) in the program memory.
(2) Indirect subroutine call (“CALL @AR”)
The top address of the subroutine that can be called by the indirect subroutine call instruction is in the
area of addresses 0000H to 0FFFH, i.e. all the addresses of the program memory.
Also refer to 5.3 Address Register (AR).
2.4.3 Table referencing
Addresses that can be referenced by the table reference instruction (“MOVT DBF, @AR”) are in the area of
addresses 0000H to 0FFFH, i.e. all the addresses of the program memory.
Also refer to 5.3 Address Register (AR) and 9.2.2 Table reference instruction (“MOVT DBF, @AR”).
Data Sheet U10101EJ4V0DS
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